1. Field of the Invention
The present invention relates generally to voltage boosting circuits, and more particularly to an improved voltage boosting circuit for a DRAM, and to an operating method thereof.
2. Description of the Background Art
Voltage boosting circuits which generate output signals boosted to be higher than a supply voltage have been employed in semiconductor integrated circuit devices such as semiconductor memory units. For example, as shown in FIGS. 1A and 1B, in a dynamic RAM 100 using a one-transistor one-capacitor type memory cell MC formed of an information storing capacitor C and an MOS field-effect transistor Q for address selection (hereinafter referred to as MOSFET), a voltage boosting circuit 101 is provided for boosting a selected level of a word line WL, coupled to the gate of the above mentioned MOSFET Q for address selection, to a higher level than that of a supply voltage. This voltage boosting circuit 101 is provided in a word line driver WLD in FIG. 1A. The voltage boosting circuit 101 is provided in order to raise a level of the gate (word line) of the MOSFET for address selection in the above mentioned memory cell to a higher level than that of the supply voltage, and prevent a high level for writing or rewriting into a memory capacitor C from being lowered by a threshold voltage of the MOSFET Q, thereby rapidly and efficiently transmitting a signal to a data line in reading information from the memory cell MC. That is, in case that the voltage boosting circuit 101 is not provided, since a potential for writing in the memory cell MC is low in writing, a long refresh time is required. Meanwhile, since a potential for reading from the memory cell MC is low in reading, an amplification sensitivity is degraded in a sense amplifier SA, resulting in erroneous reading. Further, in reading, the low potential for reading from the memory cell MC requires a time-consuming amplification at the sense amplifier SA, resulting in a delay in access time.
Furthermore, it sometimes occurs that a voltage boosting circuit is provided in order to increase the gate voltage of an output transistor comprised in an output buffer (included in a main amplifier MA in FIG. 1A) to be higher than a supply voltage. In this case as well, the reason for providing the voltage boosting circuit is to prevent the level of the output signal from being lowered by the threshold voltage of the aforementioned output transistor, thereby rapidly and efficiently transmitting the output signal to the data output line.
FIG. 1C is a circuit diagram of an example of a conventional voltage boosting circuit disclosed in Japanese Patent Laying-Open No. 62-212997. In this figure, an N channel MOSFET 2 for precharging a node A is interposed between a power supply line 1 and the node A. The gate of the N channel MOSFET 2 is supplied with a timing signal .phi..sub.1 for determining the timing of precharging. The timing signal .phi..sub.1 is generated in a control circuit 102 in FIG. 1A. A P channel MOSFET 3 and an N channel MOSFET 4 being connected in series are interposed between the node A and ground 5. Respective gates of the P channel MOSFET 3 and N channel MOSFET 4 are provided with an input signal .phi..sub.X. Also, the P channel MOSFET 3 has its source and substrate connected to each other to prevent latch up. The P channel MOSFET 3 and N channel MOSFET 4 constitute a so-called CMOS inverter to provide an output signal .phi..sub.X inverted from the input signal .phi..sub.X for an output signal line 6. In addition, one electrode of a capacitor 7 is connected to the node A. This capacitor 7 is a boosting capacitor for boosting a potential of the node A, and the other electrode thereof is supplied with a timing signal .phi..sub.2. This timing signal .phi..sub.2 is generated in the control circuit 102 in FIG. 1A. Wiring capacitance 8 is parasitic on the output signal line 6.
FIG. 2 is a timing chart for the operation of the conventional voltage boosting circuit shown in FIG. 1C. The operation of the conventional voltage boosting circuit shown in FIG. lC will be described hereinafter, referring to the timing chart of FIG. 2.
First of all, since the timing signal .phi..sub.1 is at an "H" level in an initial state, the N channel MOSFET 2 is on and the potential of the node A is (Vcc-V.sub.th). The V.sub.cc is a supply voltage and the V.sub.th is a threshold voltage of the N channel MOSFET 2. When the input signal .phi..sub.X is at the "H" level as shown in FIG. 2, the output signal .phi..sub.X is at an "L" level. When the timing signal .phi..sub.1 then goes to the "L" level, the N channel MOSFET 2 is turned off. Consequently, the node A turns to be at a floating state while being charged to (V.sub.cc -V.sub.th) When the input signal .phi..sub.X then goes to the "L" level, the P channel MOSFET 3 is turned on and the N channel MOSFET 4 is turned off, so that a charge stored in the node A is divided in capacitance into the boosting capacitor 7 (a capacitance value thereof is C.sub.1) and the wiring capacitance 8 (a capacitance value thereof is C.sub.x), and the potential of the node A, (V.sub.cc -V.sub.th) is lowered to the potential of V shown below. ##EQU1##
When the timing signal .phi..sub.2 goes to the "H" level, the potential of the node A is (V+.alpha.) and that of the output signal .phi..sub.X is also boosted to (V+.alpha.) due to the capacitive coupling of the boosting capacitor 7. At this time, the N channel MOSFET 2 is turned off, so that no charge stored in the node A flows into the power source.
As the length of the output signal line 6 increases, the capacitance value C.sub.x of the wiring capacitance 8 increases in the voltage boosting circuit shown in FIG. 1. As apparently seen in the above expression (1), the larger the capacitance value C.sub.x of the wiring capacitance is, the lower the potential V of the node A is, so that the potential (V+.alpha.) of the boosted output signal .phi..sub.X is also lowered. The capacitance value C.sub.1 of the boosting capacitor 7 need be large in order to raise the boosting level of the output signal .phi..sub.X. However, as the degree of integration in a semiconductor integrated circuit device becomes higher, it would be much more difficult to incorporate a capacitor having such a large capacitance value within the device. Further, even if the capacitance value C.sub.1 can be larger, the size of the MOSFET included in a peripheral circuit which drives the boosting capacitor 7 must be large, so that the area occupied by the peripheral circuit on a semiconductor chip is increased.
In addition, timing signals .phi..sub.1 and .phi..sub.2 are required for the conventional voltage boosting circuit shown in FIG. 1C, so that a circuit for producing these timing signals .phi..sub.1 and .phi..sub.2 need be provided in the semiconductor integrated circuit device. As a result, a problem also arose that the size of the device need be increased.